Riscv

Simulated RISC-V Processor

I created a schematic and designed a simulation for a RISC-V pipelined processor in my Computer Organization class. This involved writing the logic for all stages, fetch, decode, execute, memory, and writeback. This also included never jump branch prediction, and memory/writeback bypassing. I would say this was a team effort as much of the simulation was already coded for me, but much of the instruction definition and stage logic was left for me to figure out. This shows not only a competency with the C language, but also an understanding of the control and data flow of a RISC-V processor.